In a typical integrated system, such as a memory system, data is transferred between devices based on one or more clock signals provided to (e.g. applied to and/or generated by) the integrated system. In particular, data must be provided to devices at proper times relative to rising and/or falling edges of clock signals to ensure that a device properly captures data. In more modern systems, clock speeds have continued to increase. As a result, the duration that data placed on a bus may be considered valid has decreased. Moreover, due to disparities in performance between memory and logic transistors, scaling bandwidth between chips to desired levels has become an increasingly difficult task.
One approach that has been used to address increasing clock speeds has been the use of multi-level signaling. In multi-level signaling a single signal may be used to represent multiple bits of data, and as a result, clock speeds over particular busses may be decreased without decreasing bandwidth, or alternatively, bandwidth can be increased without increasing clock speed. That is, in systems utilizing multi-level signaling, multi-level drivers provide multi-level signals over busses having a voltage that corresponds to one of 2X (X>1) particular levels at rising and/or falling edges of clock signals, with each of the levels representing multiple bits of data. As a result, data throughput for a given frequency may be increased by a factor of X or bandwidth may be maintained using a lower frequency.
However, utilizing multi-level signaling in memory systems is not without its drawbacks, as using multi-level signals can consume more power in comparison to systems that do not use multi-level signals. Moreover, because power consumed in multi-level signaling is dependent on patterns of data provided by multi-level drivers, some patterns of data can result in higher power consumption than for other patterns of data.